So here is my first Verilog program. Please be nice but I welcome your comments. The code is designed for the Digilent Spartan 3E Xilinx development board. The code was written in Xilinx ISE version 9.x but can easily be ported to ISE version 10.x by suppressing four warnings in regards to the button triggers.
The operation is pretty straight forward once you program the board. Use the eight user switches on the development board and then press one of the four buttons. Each button corresponds to an output on the JA port. When you press the one of the buttons the current value on the switches will set the duty cycle of the PWM (Pulse Width Modulation) output on the desired output pin.
The PWM code is set to run at approximately 25 KHz when the system clock jumper is set to 50MHz.
| Attachment | Size |
|---|---|
| mpare_pwm.zip | 1.31 MB |
Recent comments
6 days 21 hours ago
6 days 21 hours ago
6 days 23 hours ago
1 week 6 days ago
2 weeks 5 days ago
2 weeks 6 days ago
2 weeks 6 days ago
8 weeks 6 days ago
12 weeks 4 days ago
13 weeks 4 days ago